THE VLSI HOMEPAGE

This page has a list of technical papers that contain useful information on ASIC Design written by well-known consultants/authors. The reader is strongly recommended to read these papers and benefit from them.

Digital Design

• The Ten Commandments of Excellent Design by Peter Chambers

• The Ten Commandment of Excellent Design - VHDL Code Examples

• Xilinx Design Reuse Methodology for ASIC and FPGA Designers

• Standard Gotchas: Subtleties in Verilog and SystemVerilog That Every Engineer Should Know

• State machine design techniques for Verilog and VHDL by Steve Golson

• On-line Verilog HDL Quick Reference Guide (Sutherland HDL)
  

• Verilog Code writing Guidelines by Rajesh Bawankule
  

Sunburst Design Papers - Cliff Cummings

• RTL Coding Styles That Yield Simulation and Synthesis Mismatches

• Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!

• “full_case parallel_case”, the Evil Twins of Verilog Synthesis

• Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs

• Synchronous Resets? Asynchronous Resets? I am so confused!
  How will I ever know which to use?

• Simulation and Synthesis Techniques for Asynchronous FIFO Design

• Verilog Nonblocking Assignments With Delays, Myths & Mysteries

Verification

• State Machine Coverage Using Specman by Jacob Joseph

• Shotgun ‘e’ Verification by Peet James

• The Five-Day Verification Plan by Peet James

Synthesis

• My Favorite dc_shell Tricks by Steve Golson

• Synthesis of a Million Gates by Don Mills

• The Human ECO Compiler by Steve Golson

Static Timing Analysis

• My Head Hurts, My Timing Stinks, and I Don’t Love On-Chip Variation by Matt Weber

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