http://vlsihomepage.com A Practical guide to VLSI Design and Verification.. Tue, 22 Apr 2008 06:30:12 +0000 http://backend.userland.com/rss092 en I stumbled upon Steve Golson's very informative and elaborate paper on ECOs (Engineering Change Order) in design. I am adding this paper to the recommended reading section, please do check it out.Share This http://vlsihomepage.com/2008/04/22/ecos-in-design/ Primetime offers several constructs to report design statistics such as clocks, max fanout, transition and capacitance, constraint checks and timing. This post will cover constructs that are used often to extract useful information from Primetime for design analysis. Design Information report_design provides a summary on operating conditions, ... http://vlsihomepage.com/2007/12/08/primetime-reports-generation/ Synopsys Primetime supports several constructs to constrain clocks in a design. In this post, we will cover a few of the most commonly used commands and their usage while running STA on a design. Clock definitions All clock characteristics such as the period (default is ns), duty cycle and clock source can ... http://vlsihomepage.com/2007/12/01/constraining-clocks-in-primetime/ Synopsys Primetime is widely used in static timing analysis of full chip gate level designs to close timing prior to tapeout. A typical primetime flow with design inputs is shown below. Static Timing Analysis Flow using Primetime Primetime is capable of analyzing multi-clock asynchronous/synchronous designs with internally generated clocks ... http://vlsihomepage.com/2007/11/18/static-timing-analysis-using-primetime/ SystemVerilog allows tasks and functions to be declared within interface definitions known as interface methods. The task or function has the same syntax as when declared in a module. Using these interface methods, the communication protocol details can be embedded within the interface definition itself. [sv] interface ahb_bus (input logic ahb_hclk, ahb_hresetn); ... http://vlsihomepage.com/2007/10/23/interfaces-in-systemverilog-2/