ECOs in Design
I stumbled upon Steve Golson’s very informative and elaborate paper on ECOs (Engineering Change Order) in design. I am adding this paper to the recommended reading section, please do check it out.
Sphere: Related ContentInertial and Transport Delays & the Event Queue in Verilog
Simulation cycle consists of two phases - a signal update phase where the simulation time is moved to the earliest scheduled transaction and values in all transactions scheduled for this time are applied to their corresponding signals and a process evaluation phase where signal assignments trigger events and all processes responding to these events are executed.
Scheduling and assigning signal values largely depends on the delay mechanism used. Transport Delay models are ideal and any change in the input is propagated to the output, no matter how small the duration of the change. Any pending transactions on a driver that are scheduled for a time late than or equal to the new transaction are deleted.
Transport Delay Illustration
Inertial Delay models depict real hardware and any change in input value is propagated to the output only if the change is stable for a duration greater than the propagation delay of the model. An inertially delayed signal assignment involves looking at pending transactions when adding a new transaction.
All transactions scheduled for a time equal to or later than the current transaction (t1) are deleted as in transport delay model. If the pulse rejection time is tr, any pending transactions between t1-tr and tr driving the current transaction value are retained and all other transactions are removed.
Inertial Delay Illustration
Verilog
The Verilog event queue is logically segmented into five different regions. Events are added to any of the five regions but are only removed from the active region.
- Events that occur at the current simulation time and can be processed in any order. These are the active events. Blocking assignments, evaluation of RHS of nonblocking assignments, conitnuous assignments, $display commads are executed in this queue.
- Events that occur at the current simulation time, but that shall be processed after all the active events are processed. These are the inactive events. Blocking assignments with #0 delays fall in this category, they are not recommended as they add unnecessary events in the queue and make simulations run slower. For more details, please refer to Cliff Cummings paper on NonBlocking Assignments.
- Events that have been evaluated during some previous simulation time, but that shall be assigned at this simulation time after all the active and inactive events are processed. These are the non blocking assign LHS update events.
- Events that shall be processed after all the active, inactive, and non blocking assign update events are processed. These are the monitor events. $monitor and $strobe are executed in this queue.
- Events that occur at some future simulation time. These are the future events. Future events are divided into future inactive events, and future non blocking assignment update events.
The processing of all the active events is called a simulation cycle.
Sphere: Related ContentSerial to Parallel and Parallel to Serial conversion
Serial to Parallel conversion is common in designs where the clock runs at slower frequency than the incoming serial stream. To maintain the throughput, the serial data is converted to parallel data. Similarly, high speed parallel data can be converted to serial stream before output from a chip - as it is very hard to manage skew between different data lines.
We will look at verilog
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module serial_to_parallel ( parallel_out, serial_in, shift_enable, clock, reset_n);
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parameter SIZE = 4;
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output [SIZE-1] parallel_out;
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input serial_in;
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input shift_enable;
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input clock;
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input reset_n;
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reg [SIZE-1] parallel_out;
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always @(posedge clock or negedge reset_n) begin
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if (~reset_n)
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parallel_out <= 0;
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else if (shift_enable)
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parallel_out <= {serial_in, parallel_out[SIZE-1:1]};
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end
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endmodule
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module parallel_2_serial (serial_out, parallel_in, load_enable,shift_enable, clock, reset_n);
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parameter SIZE=5;
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output serial_out;
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input clock;
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input reset_n;
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input load_enable;
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input shift_enable;
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input [SIZE-1:0] parallel_in;
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reg [SIZE-1:0] parallel_r;
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always @(posedge clock or negedge reset_n) begin
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if (~reset_n)
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parallel_r <= 0;
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else if (load_enable)
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parallel_r <= parallel_in;
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else if (shift_enable)
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parallel_r <= {1'b0, parallel_r[SIZE-1:1]};
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end
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assign serial_out = parallel_r[0];
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endmodule