THE VLSI HOMEPAGE

Synopsys Primetime supports several constructs to constrain clocks in a design. In this post, we will cover a few of the most commonly used commands and their usage while running STA on a design.

Clock definitions

All clock characteristics such as the period (default is ns), duty cycle and clock source can be specified using create_clock command. The syntax is as shown below

create_clock -name <clk_name> -period <clk_period> -waveform \
{rise_edge fall_edge} <clock_source>

For example to create a clock running at 125 MHz with 50% duty cycle at a PLL output,

create_clock -name clk -period 8.0 -waveform {0 4} [get_pins pll/clkout]

Internally generated clocks such as divide_by_2, (or multiply_by) can be specified using the create_generated_clock construct.

create_generated_clock -name clk_div2 -source [get_pins pll/clkout] \
-divide_by 2 [get_pins clk_divider_reg/q]

Note that we define the clock source using the -source switch at the pin instead of using the clock source name itself.

Sometimes it may be necessary to define divided down clocks using edges such as divide_by_3 clock without 50% duty cycle. Primetime offers “-edges” switch to line up the divided down clock edge with it’s source edge.

create_generated_clock -name clk_div2 -source [get_pins pll/clkout] -edges {0 16 24} \
[get_pins clk_divider_reg/q]

In addition, Primetime also allows definition of an inverted clock wrt the clock source using the -invert switch

create_generated_clock -name clk_div2 -source [get_pins pll/clkout] \
-divide_by 2 [get_pins clk_divider_reg/q] -invert

Primetime also offers the capability to define virtual clocks in the design. A virtual clock has no source and is helpful in constraining inputs and outputs where we use ideal clocks with no insertion delay.

create_clock -name clk -period 8.0 -waveform {0 4}

Clock latency, uncertainty and propagated clocks

A clock tree insertion delay can be specified using set_clock_latency command - this construct would be useful in timing a design during early stages of design where the clock tree is not yet inserted and all you have are estimates.

set_clock_latency <insertion_delay> <-source> <-early or -late> \
-rise or -fall> [get_clocks <clk_name>]

set_clock_latency 3.0 -source -early -rise [get_clocks clk_div2]

set_clock_latency 5.0 -source -late -rise [get_clocks clk_div2]

Using the “-source” switch, one can specify the clock source latency at the clock pin (for example, in the divide_by_2 clock case, a source latency to the clk_divider_reg/clk flop can be specified from the pll output). The -early and -late switches are to account for uncertainty in the clock latency (primetime uses the conservative number for each startpoint/endpoint). In addition, we can specify separate source latencies for rise and fall edges.

Clock uncertainty accounts for clock jitter, marginal errors in backannotation and any skew between two clocks.

set_clock_uncertainty -setup 0.2 [all_clocks]

set_clock_uncertainty -hold 0.1 [all_clocks]

set_clock_uncertainty 2.0 -from [get_clocks clka] -to [get_clocks clkb]

Finally, you can also make the clocks propagate through the clock tree and Primetime can calculate the insertion delay or create an ideal clock with clock latency while timing the design.

set_propagated_clock [all_clocks]

set_ideal_clock [get_clocks clk]

Clock gating checks and exclusive groups

For gated clocks, Primetime supports constraints for setup or hold violations on the gated clock to ensure that the clock is not clipped off. This ensures that the controlling signal remains stable much before or after the clock edge goes active.

set_clock_gating_check -setup 0.5 -hold 0.1 [get_clocks clk]

Apart from this, when there is no interaction between two different clocks, they can be defined as exclusive to each other for faster timing analysis. For example, to declare that clk and clk2 are exclusive to clk3 or clk4,

set_clock_groups -exclusive -group {clk clk2} -group {clk3 clk4}

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