THE VLSI HOMEPAGE

Synopsys Primetime is widely used in static timing analysis of full chip gate level designs to close timing prior to tapeout. A typical primetime flow with design inputs is shown below.

Static Timing Analysis Flow using Primetime

Primetime is capable of analyzing multi-clock asynchronous/synchronous designs with internally generated clocks and timing exceptions. Multi-corner analysis (fast, slow, bc/wc) and on-chip variation with signal integrity checks (crosstalk) is also supported in Primetime. Primetime supports

• Maximum/minimum capacitance, fanout and transition checks
• Setup/hold/recovery and removal checks
• Reports clock insertion delays, skew, clock gating check violations and data checks

Primetime inputs include

• Library database in standard .db format - the library elements include technology standard cell and IO library (65 nm/130 nm), hard macros like PLLs, SERDES and any custom cells. The libraries are characterized in slow and fast corners to run analysis in multiple corners.

• Design constraints in SDC format - clock definitions, timing exceptions, case analysis and IO constraints. Usually, a design supports multiple modes where the clock can run at different frequencies depending on the mode. Case analysis constraints propagate the appropriate path for each mode, also DFT mode runs are also supported.

• Timing models for blocks or analog blocks like PLL to make run times faster and factor in timing characteristics. Timing models can be
  • Quick Timing Model - a preliminary timing model created using PT.
  • ILM (interface logic model which includes only the first stage of flops surrounding the IOs and the guts of the block is all blackboxed),
  • Extracted timing model that includes only timing arcs between inputs and outputs
  • Stamp model that defines the timing in a standard descriptive format.
• Routed netlist from physical design in VHDL/Verilog or db format.

• Parasitics - Interconnect Delay in SPEF/DSPF format and cell delay in SDF format.

• Incremental delays in SDF format from crosstalk analysis

Primetime breaks down the design into multiple timing paths with one startpoint (flop/input port) and one endpoint (flop/output port). Setup/Hold checks and IO checks are covered in earlier posts, we will cover commonly used primetime commands in our next post.

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