THE VLSI HOMEPAGE

Verilog supports variable and net types that are identical to each other and drive four-state values.

• reg, integer, time variables can have ‘0′, ‘1′, ‘Z’ and ‘X’ values

• wand , wor , wire net types can have ‘0′, ‘1′, ‘Z’ and ‘X’ values with 7 strengths giving 120 values

SystemVerilog (SV) extends Verilog variable types that can be either 2-state (’0′ or ‘1′) or 4-state (’0′, ‘1′, ‘X’, ‘Z’) data types while net types can be only 4-state data types. Data declarations in SystemVerilog have a type (that indicates if the signal is a net or a variable) and a data type (that indicates if it is 2-state or 4-state values).

SV Four state logic type

To replace the confusing reg type in Verilog, SystemVerilog defines a 4-state logic data type that can be associated with variables or nets. For example,

var logic [31:0] data; // a 32-bit variable supporting 4-state values

wire logic [31:0] data; // a 32-bit net capable of driving 4-state values.

Note that Verilog reg type cannot be associated with net types while SV logic type can be. Also note that the variable is implied if var keyword is absent in a declaration i.e.

logic [31:0] data // is same as var logic [31:0] data

Similarly, if the var is explicitly defined but the datatype is absent, it is assumed to be logic data type by default.

var [31:0] data // is same as var logic [31:0] data

wire [31:0] data; // a 32-bit net type, 4-state logic datatype.

SV Two state types

SV adds new 2-state types that can aid faster simulations and also consume less memory while modeling hardware at higher levels. These include

• bit - a single bit 2-state integer, user-defined vector size

var bit flag; // -bit wide 2-state variable

var bit [31:0] count; // a 32-bit 2-state variable

• byte - a single byte 2-state integer
• shortint - a 16-bit 2-state integer
• int - a 32-bit 2-state integer, similar to C
• longint - a 64-bit 2-state integer

The byte, int, longint, shortint types are signed by default, SV includes unsigned keyword to override this default.

int unsigned data; // Unsigned 32-bit variable

The 4-state variables if uninitialized take a value of ‘X’ until the first assignment - it is the recommended choice for synthesizable RTL. 2-state variables if uninitialized default to ‘0′. When a 4-state variable is assigned to a 2-state variable, the ‘X’ and ‘Z’ are translated to ‘0′. 2-state variables are synthesized similar to the 4-state variables by tools that ignore the default value of zero.

Abstract Data Types (not synthesizable) such as real (similar to Cdouble), shortreal (C float), void (used to define functions that do not return any value or in tagged unions) are also supported in SV.

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Literal Values
SystemVerilog extends built-in data types and literal values available in Verilog. Literals can be integer, real, time, arrays or string.

• Integer and logical literals (useful for Designers)

In Verilog, semantics exist to scale assigned values of "0", "x" and "z" to a vector. However, no option exists to expand a value of "1" if needed.

SystemVerilog allows the ability to specify unsized literal values without base specifiers (like binary, hex or octal) and scale a value of '1' in unsized vectors.

'1 // set all bits on LHS to 1
'0 // set all bits on LHS to 0
'x or 'X // set all bits on LHS to x
'z or 'Z // set all bits on LHS to z

This feature is very useful when using parameterized variables since you only need to change the parameter size instead of the entire code. (see example below)

• Time literals
  

Time can be represented as integer or real without any space between the unit (fs ps us ms s step) and the number. For example, 0.2ms or 100ns. In Verilog, the first `timescale directive remains in effect for all modules until a new ` timescale is encountered - this creates a dependency on the order in which files are read in. If a verilog source file without ` timescale is read before or after the second `timescale directive, different units will be in effect. By specifying the unit as part of the declaration, any ambiguity to the timescale is resolved.

Further, SystemVerilog supports timeunit and timeprecision keywords that can be used to locally bind a module or interface to the time units. These units must be declared immediately following the module port list definition without any declarations or assignments in between. For example,

• Real Literals

Any floating or exponential numbers are represented as real literals. For example, 2.5 and 4e11

• String Literals

A string literal is enclosed in quotes and has it's own data type. For example, byte C1 = "B"; In addition, SystemVerilog also defines a string datatype to which a string literal can be assigned.

• Array Literals

Array literals are similar to C but replicators {{ }} are allowed and can be nested. For example,

int array_a [1:0] [2:0] = {2{{3{1,2}}}} ; // same as { {1,2,1,2,1,2}, {1,2,1,2,1,2} }

• Structure Literals

Similar to C syntax, an example is below. We will look at these in detail in later posts.

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Various type of timing variations make accurate modeling of interconnect and circuits very hard as we move to nanometer processes. In traditional static timing analysis, based on process parameter files we characterize the cells, calculate the cell delays and crosstalk effects and run timing analysis. This however hides the silicon process variations from the designer.

These variations are broadly classified into Process variations (due to fabrication such as oxide thickness, transistor width, effective channel length etc.) and Environmental variations (temperature and voltage variations).

Process variations is further classified into Inter-die variations that vary from die to die and affect all the chips on the die in an exact similar way and Intra-die variations that may cause variations within a single chip or between chips on the same die.

To account for the inter-die variations, timing analysis at multiple different corners are run on the chip. But as we move towards nanometer processes, intra-die variations are significant and very complex to be captured in traditional STA as each region within a chip can use different process corner.

To overcome this limitation, an alternative approach known as Statistical Static Timing Analysis is proposed where the delays are not represented as fixed numbers but as probability density functions (pdf) taking the statistical distribution of variations into account.

In traditional timing analysis, the delay at the gate outputs are computed using "sum" of gate delay and delay at the gate input. Once all the component delays have been determined, a "max" operation gives the maximum arrival time at the output. SSTA is similar to STA except that the interconnect delays and cell delays are probability density functions (pdf like Gaussian Model) instead of numbers.

SSTA can again be broadly classified into path-based methods (find pdf on a path-by-path basis and then perform statistical add operation to find the delay distribution) and block-based methods (perform critical path analysis, processing each gate once but much faster than path-based methods if the number of paths are relatively large).

Monte-Carlo simulations is the most simple method for SSTA where given an arbitrary distribution, the tool generates sample points and runs analysis at each sample point and aggregates the results to find the delay distribution. The major disadvantage is the larger runtimes required.

Another complication in SSTA is to account for spatial corelations within a single chip - partition the chip into x by y grids, each grid modeled using corelated variables.

Several SSTA techniques have been proposed and it is still at a nascent stage - IBM recently announced a set of statistical timing analysis tools for 45 nm and below.

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