Procedural Blocks in SystemVerilog
Verilog
SystemVerilog adds three new procedural blocks - always_ff, always_comb and always_latch for clear logic inference.
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always_comb // Not necessary to specify sensitivity list
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if (sel)
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out = in1;
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else
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out = in2;
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always_latch // infer latch
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if (en) q <= d;
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always_ff @(posedge clk, negedge rstn)
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if (!rstn) q <= 0;
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else q <= d;
There are three key differences between always_comb and always blocks :
- the variables on the LHS side of assignments in always_comb blocks cannot be assigned in multiple procedural blocks for true combinatorial logic behavior and
- the always_comb block is automatically triggered at simulation time 0 after all initial and always blocks are active. This is necessary to prevent simulation deadlock that would exist if one were to use 2-state types in the always block that default to zero.
- when including function calls inside always_comb blocks, Verilog always @* can infer incomplete sensitivity lists since it only adds signals read directly in the block and not any inputs called by the function. SV infers the sensitivity list correctly and supports calling functions without arguments.
Tasks and Functions
SV adds several enhancements to Verilog tasks and functions that include:
- A return keyword that returns the value of the function. In verilog, the value assigned to the function name is returned. In SV, the return takes precedence over this. In addition, the return keyword can be used to abort the function at any time whereas in Verilog the function is executed until the endfunction is reached.
- SV adds a void type to declare functions that have no return value.
- SV infers begin - end for grouping multiple statements in functions and tasks.
- SV allows function formal arguments to be input, output, inout or ref unlike Verilog where function arguments can only be input. By default, all arguments are input in SV unless explicitly declared otherwise.
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function automatic int expo (input int a = 2, b); // arguments can have default values
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expo = a * b;
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return a ** b; // return overrides the value written to function name expo
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endfunction
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always_comb
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x = expo (.a (m), .b(n) ); // can pass function arguments by name in SV
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// allows unpacked arrays, packed/unpacked structures in functions/tasks
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typedef struct {
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logic [23:0] addr;
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logic [127:0] data;
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byte crc;
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} packet_s;
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function void packet_construct ( input logic [127:0] data_in, output packet_s pkt_s );
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pkt_s.data = data_in;
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endfunction
SV allows passing arguments by value and by reference to a function or a task. Pass by argument works by copying the argument into the subroutine area and any changes to the copy are only locally visible. To pass by reference, SV uses the ref keyword and the argument is not duplicated within the function or task and any changes within the subroutine is also visible to the function call. In order to have ref arguments, the function or task must be automatic.
Sphere: Related ContentArrays in SystemVerilog
An array is a collection of similar variables, accessible via indices and the array name. Verilog
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reg r [0:63]; // 1 dimensional unpacked array
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wire [0:7] count [0:144]; // a 1-dimensional unpacked array 145 8-bit nets
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int i [0:7] [0:15]; // a 2-dimensional unpacked array
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// Packed Arrays
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wire [3:0] count; // packed array of 4-bits
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wire [3:0] [1:0] addr; // 2-dimensional packed array
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wire [7:0] addr_out = addr; // entire packed array
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// Initializing Packed array
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wire [7:0] [1:0] data = 16'h0;
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// Initializing Unpacked array
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wire data [0:1] [0:3] = '{ '{11, 12, 13, 14}, '{2, 3, 4, 5} }
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int addr [0:1] [0:15] = '{ default: 2'h3 } // initialize all elements to 2'b11
SV extends the unpacked arrays to new types like int, shortint, logic, bit, byte, real and shortreal. SV also allows accessing all elements of an array at a time unlike Verilog. For packed arrays, multi-dimensional arrays are supported by SV. The entire packed array is stored as contiguous order of bits and arithmetic/logical operations are supported.
Packed arrays can be assigned to another packed array even if their sizes do not match. However, unpacked arrays can be assigned to another unpacked array only if the vector and dimension size are equal. To assign an unpacked array to a packed array or vice versa, bit stream casting needs to be done. A bit-stream cast converts an unpacked array into a stream of bits using the SV static cast operator '. Both packed and unpacked arrays are synthesizable.
SV also supports dynamic arrays for higher levels of modeling (not synthesizable) - A dynamic array is one dimension of an unpacked array, the size of which is set or changed during runtime.
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bit [3:0] crc [];// Dynamic array of 4-bit vectors
SV supports new[], size() and delete() methods similar to C for dynamic arrays.
Associative arrays are also supported by SV - the array index is not restricted to integral values (like int, shortint) and can be any data type.
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integer assoc[*]; // * is wildcard indicates unspecified but integral value index
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bit [7:0] assoc [string]; // indexed by string
SV supports in-built methods for associative arrays as tabulated below.
Associative Methods |
Description |
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<array>.num( )
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Returns number of entries in the associative array. |
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<array>.delete(N)
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if index N is not specified, deletes all elements of the |
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<array>.exists(N) |
checks if element exists at that particular index of the array. returns 1 if true. index is mandatory |
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<array>.first(N) |
assigns to the index variable N the value of the smallest |
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<array>.last(N) |
assigns to the index variable N the value of the largest index in the array, returns 1 if array is not empty, 0 otherwise |
| <array>.next(N) | finds the entry whose index is greater than current index N and assigns the index variable to that next entry. Retruns 1 if true |
| <array>.prev(N) | finds the entry whose index is smaller than current index N and assigns the index variable to that previous entry. Retruns 1 if true |
Structures and Unions in SystemVerilog
SystemVerilog supports C-like structures without the optional tag before braces using struct keyword to group several related signals together.
Both variable and net types can be defined as structures. However, net types cannot be used for members of structures. By default, all structures are variable types. Structures that are defined without typedef are known as anonymous structures.
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// Anonymous Structure
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struct {
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pkt_type_t type;
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bit [15:0] addr;
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bit [ 31:0] data;
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byte crc;
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} Packet_s;
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// To assign a value to a struct member
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Packet_s.type = ETHER_II;
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// User defined struct
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typedef struct {
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pkt_type_t type;
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bit [15:0] addr;
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bit [ 31:0] data;
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byte crc;
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} Packet_s;
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Packet_s pkt;
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// To assign a value to a struct member
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pkt.type = ETHER_II;
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// Structures can be initialized using '{ and } operators
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Packet_s pkt = '{ETHER_II, 16'h40, 32'hffff, 8'b30};
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// Alternate way - explicit
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Packet_s pkt = '{crc: 8'b30, addr:16'h40, data:32'hffff, type:ETHER_II};
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// Default to zero using default keyword
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Packet_s pkt = '{default:0};
structures are unpacked by default but packed structures are also possible using packed keyword after the struct - the members are stored as a bit vector with the first member being the MSB. Packed structures can compass only integral values (byte, int, shortint, logic or bit) - real types, enum types are not allowed. This allows mathematical/logical operations on packed structures. packed structures can be either signed or unsigned.
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typedef struct packed signed {
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logic [7:0] addr;
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logic [31:0] data;
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byte crc;
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} Packet_s;
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Packet_s pkt_a, pkt_b;
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always @(posedge clock)
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if (pkt_a < pkt_b) // Arithmetic signed operation
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..
Structures can be passed through modules and also passed as arguments to tasks and functions if they are not anonymous. structs are also synthesizable.
Unions are supported in SV using union keyword and stores only a single value unlike structures. Unpacked unions can consist of any variable type like real, unpacked structs for abstract modeling and are not synthesizable.
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typedef union {
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logic [3:0] data;
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logic data_valid;
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} data_u;
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data_u data_ctrl_u;
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//tagged union
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typedef union tagged {
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logic [3:0] data;
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logic data_valid;
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} data_u;
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data_u data_ctrl_u;
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data_ctrl_u = tagged data_valid 1; // set data_valid in union data_ctrl_u to 1
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data_valid_out = data_ctrl_u.data_valid;
unions can be tagged to include a member with implicit tag - this tag represents the name of the union member last written to. Values are stored in tagged unions using a tagged expression.
unions can also be packed - the members must have same number of bits making them synthesizable.
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