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Interfaces in SystemVerilog - 2

Posted in SystemVerilog by Nigam on the October 23rd, 2007

SystemVerilog allows tasks and functions to be declared within interface definitions known as interface methods. The task or function has the same syntax as when declared in a module. Using these interface methods, the communication protocol details can be embedded within the interface definition itself.

PLAIN TEXT
SV:
  1. interface ahb_bus (input logic ahb_hclk, ahb_hresetn); // Interface can have ports.
  2.    wire [31:0]     ahb_hdata;
  3.    wire [31:0]     ahb_addr;
  4.    logic              ahb_hwrite;
  5.    logic [1:0]      ahb_htrans;
  6.    logic [2:0]      ahb_hsize;
  7.    logic [2:0]      ahb_hburst;
  8.    logic              ahb_hready;
  9.    logic [1:0]      ahb_hresp;
  10.  
  11. // Task defined internal to interface
  12.    task slave_read ( input logic [31:0] raddr);
  13.    // ...
  14.    endtask
  15.  
  16. endinterface

Interface methods can also be imported if they are not defined within the interface definition itself. If an interface is connected using modport construct, then the import keyword is used to specify the method. Alternative way is to add the task keyword next to the import and also include function arguments - this is required if the task is exported from an external module.

PLAIN TEXT
SV:
  1. interface ahb_bus (input logic ahb_hclk, ahb_hresetn); // Interface can have ports.
  2.    wire [31:0]     ahb_hdata;
  3.    wire [31:0]     ahb_addr;
  4.    logic              ahb_hwrite;
  5.    logic [1:0]      ahb_htrans;
  6.    logic [2:0]      ahb_hsize;
  7.    logic [2:0]      ahb_hburst;
  8.    logic              ahb_hready;
  9.    logic [1:0]      ahb_hresp;
  10.  
  11.   modport slave ( import slave_read,   // simplest way of importing tasks
  12.                         inout ahb_hdata,
  13.                         input ahb_haddr,
  14.                         input ahb_hsize,
  15.                         output ahb_hready,
  16.                         ---
  17.                );
  18.  
  19. // Alternative explicit way
  20.    modport slave ( import task slave_read (input [31:0] addr),   // explicit
  21.                          inout ahb_hdata,
  22.                          input ahb_haddr,
  23.                          input ahb_hsize,
  24.                          output ahb_hready,
  25.                           ---
  26.                   );

Importing a task or a function through a modport gives the module access to that task by prepending the interface port name to the task name as with other variables. The imported function/task must be declared as automatic in order to be synthesizable.

SV also includes a way to export a task defined in one module to be available to other modules through an interface. For example, if a function is defined in module A and is exported in the modport construct within interface definition using the export keyword, then the task is available to module B that uses that modport. However, this is not synthesizable and we cannot export the same function from multiple instances of a module.

It is also possible to define a task or function using extern keyword without associating it with the modport construct.

PLAIN TEXT
SV:
  1. interface shb_bus (....)
  2. ---
  3.      extern check_parity (input logic [31:0] data); // Not associated with modport
  4.  
  5.      modport ahb_slave (...);
  6.  
  7. endinterface
  8.  
  9. module A (...);
  10.  
  11.   task check_parity (input logic [31:0] data);
  12.   // --
  13.   endtask
  14. endmodule

Interfaces can also contain procedural blocks like always, always_ff, parameters and generate statements similar to modules.

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