Procedural Statements and Operators in SystemVerilog
Verilog
Enhanced if-else
SV adds unique and priority keywords which can be used before an if clause. A priority if indicates that the logic will be intrepreted in the order listed - i.e. like priority encoder. A unique if indicates that all the expressions in the if-else are mutually exclusive i.e. only one of the expressions is true at any given time. These keywords make the design intent more intuitive and aid synthesis tools infer priority encoder logic only when required. If no condition matches with either of these keywords without an explicit else, it results in a runtime error.
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logic [3:0] mode_sel;
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always_comb begin
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unique if (mode_sel == 4'b0001) out = in1; // unique - mutually exclusive conditions, can be executed in parallel
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else if (mode_sel == 4'b0010) out = in2;
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else if (mode_sel == 4'b0100) out = in3;
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else if (mode_sel == 4'b1000) out = in4;
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end
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always_comb begin
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priority if (mode_sel == 4'b0001) out = in1; // priority - sequential order, first true expression takes precedence
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else if (mode_sel == 4'b0010) out = in2;
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else if (mode_sel == 4'b0100) out = in3;
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else if (mode_sel == 4'b1000) out = in4;
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end
Enhanced case statements
Similar to if-else statements, SV supports priority and unique keywords for case, casex and casez statements also. For synthesis, the unique case is similar to enabling the full_case and parallel_case pragmas and priority case is similar to enabling the full_case. However, by including these keywords in the SV language rather than use synthesis pragmas, any simulation/synthesis mismatches in how tools intrepret the logic can be avoided.
Enhanced for loops
In Verilog, the variable used in a for loop expression should be declared prior to the loop. Also, if multiple for loops are running concurrently, separate variables need to be used. SV simplifies the for loops by allowing to declare the variable in for loop expression itself.
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always_ff @(posedge clk) begin : label_count // SV allows named begin-end blocks
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for (int i = 0; i <16; i++) // automatic variable int, i visible only within for loop
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count = count + incr[i]
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end : label_count
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//foreach loop construct
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logic [15:0] parity;
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logic [15:0] [7:0] data;
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foreach (parity[i]) parity[i] = ^data[i]; // generates parity for each data byte
SV adds a foreach loop construct which can be used to iterate over elements of single and multidimensional arrays without specifying the array dimension. SV also adds continue, break and return statements like C. SV also supports labels before any procedural statement.
SV supports a final block that is executed at the end of simulation time (unlike initial time) and is used to display statistical information about the simulation using $display.
Operators
SV includes increment (++) and decrement (--) operators similar to C - they can be used to post-increment or pre-increment a variable. The increment and decrement operators behave as blocking assignments and should be used only for combinatorial blocks to avoid race conditions i.e. the ++ or -- operators should not be used in always_ff blocks.
SV supports C like assignment operators like +=, ^=, !=, *=, <<= etc. These assigment operators behave like blocking assignments like the above. SV adds two new comparison operators ==? and !=? in addition to == and === operators.
The ==? referred to as wildcard equality operator makes a bit wise comparison of two operands but any logic X or Z in the right operand is treated as a wildcard and matches any value in the LHS operand's corresponding bit position.
In addition, SV supports inside keyword to test if a variable matches anywhere within a set of values.
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logic [2:0] count;
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if (count inside (3'b001, 3'b010, 3'b100)) // similar to if ((count==3'b001) || (count==3'b010)..)
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int count [0:31];
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if (100 inside (count)); // can also be an array