Procedural Blocks in SystemVerilog
Verilog
SystemVerilog adds three new procedural blocks - always_ff, always_comb and always_latch for clear logic inference.
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always_comb // Not necessary to specify sensitivity list
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if (sel)
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out = in1;
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else
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out = in2;
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always_latch // infer latch
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if (en) q <= d;
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always_ff @(posedge clk, negedge rstn)
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if (!rstn) q <= 0;
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else q <= d;
There are three key differences between always_comb and always blocks :
- the variables on the LHS side of assignments in always_comb blocks cannot be assigned in multiple procedural blocks for true combinatorial logic behavior and
- the always_comb block is automatically triggered at simulation time 0 after all initial and always blocks are active. This is necessary to prevent simulation deadlock that would exist if one were to use 2-state types in the always block that default to zero.
- when including function calls inside always_comb blocks, Verilog always @* can infer incomplete sensitivity lists since it only adds signals read directly in the block and not any inputs called by the function. SV infers the sensitivity list correctly and supports calling functions without arguments.
Tasks and Functions
SV adds several enhancements to Verilog tasks and functions that include:
- A return keyword that returns the value of the function. In verilog, the value assigned to the function name is returned. In SV, the return takes precedence over this. In addition, the return keyword can be used to abort the function at any time whereas in Verilog the function is executed until the endfunction is reached.
- SV adds a void type to declare functions that have no return value.
- SV infers begin - end for grouping multiple statements in functions and tasks.
- SV allows function formal arguments to be input, output, inout or ref unlike Verilog where function arguments can only be input. By default, all arguments are input in SV unless explicitly declared otherwise.
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function automatic int expo (input int a = 2, b); // arguments can have default values
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expo = a * b;
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return a ** b; // return overrides the value written to function name expo
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endfunction
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always_comb
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x = expo (.a (m), .b(n) ); // can pass function arguments by name in SV
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// allows unpacked arrays, packed/unpacked structures in functions/tasks
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typedef struct {
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logic [23:0] addr;
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logic [127:0] data;
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byte crc;
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} packet_s;
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function void packet_construct ( input logic [127:0] data_in, output packet_s pkt_s );
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pkt_s.data = data_in;
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endfunction
SV allows passing arguments by value and by reference to a function or a task. Pass by argument works by copying the argument into the subroutine area and any changes to the copy are only locally visible. To pass by reference, SV uses the ref keyword and the argument is not duplicated within the function or task and any changes within the subroutine is also visible to the function call. In order to have ref arguments, the function or task must be automatic.
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