User defined Types in SystemVerilog
Verilog does not support user defined types that could be useful while modeling at higher levels of abstraction. SystemVerilog extends Verilog and offers users flexibility to create new variable and net types. User defined types allow new types to be created from existing types using the typedef command.
typedef int unsigned uint;
uint i; // unsigned integer
A user defined type can be used before it is created provided it is first defined using empty typedef.
typedef flag_t;
flag_t = '0;
typedef logic [3:0] flag_t ;
type definitions can be declared either externally or in packages or locally.
SV Enumerated Types provide a way to declare abstract variables that can have listed set of values. Syntax is
enum (enum_base_type) { enum_name_declarations } enum_name
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enum {ADD, SUB, DIVI, MUL} opcode; // ADD is assigned value 1, SUB 2, DIVI 3 and MUL 4
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enum {ADD=4, SUB, DIVI=10, MUL} opcode; // ADD is 4, SUB is 5, DIVI is 10, MUL is 11
Verilog does not support enumerated types but supports parameter and 'define macros to make the code easier to read - for example, FSM states can be defined as parameters while `define would be used to define a error condition. The disadvantage is that the state and nextstate variables can be declared using only predefined datatypes and the list of values they can take cannot be limited.
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enum logic [3:0] {IDLE = 4'b001,
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XMT_ADDR = 4'b0010,
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XMT_DATA = 4'b0100,
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WAIT_FOR_ACK = 4'b1000} State, NextState;
SV enum types limit the state variables to the enum values maintaining consistency for synthesis and simulation.
Enumerated types can also be declared as user defined type using typedef.
typedef enum {TRUE, FALSE} boolean;
boolean flag, result;
Enumerated types are strongly typed and cannot be assigned a value outside it's legal list. As a result, arithmetical operations such as state++ are illegal as it can go out of bounds. Static and Dynamic casting to an enumerated type is allowed.
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typedef enum {IDLE, XMT, WAIT, DONE} states_t;
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states_t state, next_state;
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next_state = states_t'(state++); // Legal, casting can cause out-of-bounds !!
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$cast(next_state, state + 1); // Legal, will report error if out of bounds
SV includes a set of specialized methods to enable iterations over values of the enumerated types.
| Enumerated Type Methods | Description |
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<enum_var>.first
|
returns first enum value in the list of enumerated types |
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<enum_var>.last
|
returns last enum value in the list |
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<enum_var>.next(N) |
return next value in the list. If a number is added to next, it returns the Nth next value from the current value in the list. If the Nth next value is not legal, it returns the first value in the list. |
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<enum_var>.prev(N) |
return previous value in the list. Similar to next, except if Nth previous value is not legal, returns last value in the list. |
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<enum_var>.name |
returns string representation of the label given to enum value. If label is absent, returns empty string. Can be used to display current value of enum_variable using $display. |