THE VLSI HOMEPAGE

Verilog supports variable and net types that are identical to each other and drive four-state values.

• reg, integer, time variables can have ‘0′, ‘1′, ‘Z’ and ‘X’ values

• wand , wor , wire net types can have ‘0′, ‘1′, ‘Z’ and ‘X’ values with 7 strengths giving 120 values

SystemVerilog (SV) extends Verilog variable types that can be either 2-state (’0′ or ‘1′) or 4-state (’0′, ‘1′, ‘X’, ‘Z’) data types while net types can be only 4-state data types. Data declarations in SystemVerilog have a type (that indicates if the signal is a net or a variable) and a data type (that indicates if it is 2-state or 4-state values).

SV Four state logic type

To replace the confusing reg type in Verilog, SystemVerilog defines a 4-state logic data type that can be associated with variables or nets. For example,

var logic [31:0] data; // a 32-bit variable supporting 4-state values

wire logic [31:0] data; // a 32-bit net capable of driving 4-state values.

Note that Verilog reg type cannot be associated with net types while SV logic type can be. Also note that the variable is implied if var keyword is absent in a declaration i.e.

logic [31:0] data // is same as var logic [31:0] data

Similarly, if the var is explicitly defined but the datatype is absent, it is assumed to be logic data type by default.

var [31:0] data // is same as var logic [31:0] data

wire [31:0] data; // a 32-bit net type, 4-state logic datatype.

SV Two state types

SV adds new 2-state types that can aid faster simulations and also consume less memory while modeling hardware at higher levels. These include

• bit - a single bit 2-state integer, user-defined vector size

var bit flag; // -bit wide 2-state variable

var bit [31:0] count; // a 32-bit 2-state variable

• byte - a single byte 2-state integer
• shortint - a 16-bit 2-state integer
• int - a 32-bit 2-state integer, similar to C
• longint - a 64-bit 2-state integer

The byte, int, longint, shortint types are signed by default, SV includes unsigned keyword to override this default.

int unsigned data; // Unsigned 32-bit variable

The 4-state variables if uninitialized take a value of ‘X’ until the first assignment - it is the recommended choice for synthesizable RTL. 2-state variables if uninitialized default to ‘0′. When a 4-state variable is assigned to a 2-state variable, the ‘X’ and ‘Z’ are translated to ‘0′. 2-state variables are synthesized similar to the 4-state variables by tools that ignore the default value of zero.

Abstract Data Types (not synthesizable) such as real (similar to Cdouble), shortreal (C float), void (used to define functions that do not return any value or in tagged unions) are also supported in SV.

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