Statistical Static Timing Analysis
Various type of timing variations make accurate modeling of interconnect and circuits very hard as we move to nanometer processes. In traditional static timing analysis, based on process parameter files we characterize the cells, calculate the cell delays and crosstalk effects and run timing analysis. This however hides the silicon process variations from the designer.
These variations are broadly classified into Process variations (due to fabrication such as oxide thickness, transistor width, effective channel length etc.) and Environmental variations (temperature and voltage variations).
Process variations is further classified into Inter-die variations that vary from die to die and affect all the chips on the die in an exact similar way and Intra-die variations that may cause variations within a single chip or between chips on the same die.
To account for the inter-die variations, timing analysis at multiple different corners are run on the chip. But as we move towards nanometer processes, intra-die variations are significant and very complex to be captured in traditional STA as each region within a chip can use different process corner.
To overcome this limitation, an alternative approach known as Statistical Static Timing Analysis is proposed where the delays are not represented as fixed numbers but as probability density functions (pdf) taking the statistical distribution of variations into account.
In traditional timing analysis, the delay at the gate outputs are computed using “sum” of gate delay and delay at the gate input. Once all the component delays have been determined, a “max” operation gives the maximum arrival time at the output. SSTA is similar to STA except that the interconnect delays and cell delays are probability density functions (pdf like Gaussian Model) instead of numbers.
SSTA can again be broadly classified into path-based methods (find pdf on a path-by-path basis and then perform statistical add operation to find the delay distribution) and block-based methods (perform critical path analysis, processing each gate once but much faster than path-based methods if the number of paths are relatively large).
Monte-Carlo simulations is the most simple method for SSTA where given an arbitrary distribution, the tool generates sample points and runs analysis at each sample point and aggregates the results to find the delay distribution. The major disadvantage is the larger runtimes required.
Another complication in SSTA is to account for spatial corelations within a single chip - partition the chip into x by y grids, each grid modeled using corelated variables.
Several SSTA techniques have been proposed and it is still at a nascent stage - IBM recently announced a set of statistical timing analysis tools for 45 nm and below.
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