THE VLSI HOMEPAGE

Need for SystemVerilog

As ASIC designs get complex and grow larger in size, the modeling of these designs using register transfer level languages like Verilog also scale accordingly. In addition to verify these designs, use of Hardware Verification Languages (HVL) like ‘e’ to with new semantics/concepts pose a steep learning curve. To overcome these limitations, a unified language for both design and verification based on existing Verilog standard (and backward compatible to Verilog) was conceived.

SystemVerilog (Standard IEEE 1800-2005) is based on Verilog-2005 standard and includes new, effective and useful constructs for both design and verification. It integrates high-level hardware modeling extensions to Verilog with Hardware verification language (HVL like OpenVERA, ‘e’) constructs to create a unified design and verification language - Hardware Description and Verification Language (HDVL).

Key SystemVerilog Enhancements for Design

• New hierarchical structure (interface - endinterface) for modeling at higher levels of abstraction. It encapsulates communication and protocol checking within the design eliminating any conection errors.

• Datatype extensions - SystemVerilog supports the four state (0,1,x,z) Verilog datatypes and extends it to four/two state logic, bit, int, longint datatypes. Usage of two state (0,1) datatypes like bit, int make the simulations run faster. User defined datatypes using typedef, enumerateddatatypes using enum are also supported.

• Supports static variables that are initialized at time 0, global variables that are accessible from any scope (for example, const is a global constant), local variables that are available locally (for example, localparam).

• Supports packages for sharing across different modules using package - endpackage, derived from VHDL

• Supports structures and unions similar to C to confine multiple bus signals within one structure. Also add object-oriented features from C++ like classes. Classes can be public or private and are used to define methods and properties of the object.

• Verilog task and function enhancements such as arguments can be passed by reference, functions can be void etc.

• C features like for and do loops, continue, break etc. Unpacked arrays where all or part elements of an array can copied to another array unlike Verilog that allows only one element of array to be accessible at a time.

Key SystemVerilog Enhancements for Verification

• Supports built-in class objects (semaphore and mailbox) for synchronizing parallel activities in a testbench. semaphore is arbitration of shared resources (keys) among different processes - if no key is available to a process, it can wait until required number of keys are returned to the bucket. mailbox helps in exchanging messages between processes. The message queue behaves like a FIFO.

• Supports dynamic arrays that can be restricted to a particular size during runtime and associative arrays that can be referenced using enum types as values.

• Two random number classes rand and randc that aid in constraining the random values generated for verification.

• Supports assertions conforming to Property Specification Language (PSL) standard.

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