<?xml version="1.0" encoding="UTF-8"?><!-- generator="wordpress/2.2.2" -->
<rss version="2.0" 
	xmlns:content="http://purl.org/rss/1.0/modules/content/">
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	<title>Comments on: Formal Verification</title>
	<link>http://vlsihomepage.com/2007/10/07/formal-verification/</link>
	<description>A Practical guide to VLSI Design and Verification..</description>
	<pubDate>Mon, 06 Oct 2008 16:48:06 +0000</pubDate>
	<generator>http://wordpress.org/?v=2.2.2</generator>

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		<title>By: Nigam</title>
		<link>http://vlsihomepage.com/2007/10/07/formal-verification/#comment-14</link>
		<author>Nigam</author>
		<pubDate>Fri, 12 Oct 2007 10:01:36 +0000</pubDate>
		<guid>http://vlsihomepage.com/2007/10/07/formal-verification/#comment-14</guid>
		<description>hi Rohit,

Excellent points !!  I have heard of Magellan but never used it personally.

Regarding cutpoints, I stand corrected !

I invite you to write posts based on your experience in CAD tools and design.

Keep the comments coming.

thanks,
Nigam</description>
		<content:encoded><![CDATA[<p>hi Rohit,</p>
<p>Excellent points !!  I have heard of Magellan but never used it personally.</p>
<p>Regarding cutpoints, I stand corrected !</p>
<p>I invite you to write posts based on your experience in CAD tools and design.</p>
<p>Keep the comments coming.</p>
<p>thanks,<br />
Nigam</p>
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		<title>By: RN</title>
		<link>http://vlsihomepage.com/2007/10/07/formal-verification/#comment-9</link>
		<author>RN</author>
		<pubDate>Thu, 11 Oct 2007 06:00:14 +0000</pubDate>
		<guid>http://vlsihomepage.com/2007/10/07/formal-verification/#comment-9</guid>
		<description>Most FV tools dont simulate the design. 

There are tools that support both  Simulation Static-Equivalency-checks. Magellan from synopsys comes to mind.

FV tools essentially compare logic cones between "cut points". Cut points are sequentials and primary outputs. A "logic cone" is represented as a BDD (or its present day variant - ROBDD).

Simulation tools are completely different. They compile your design into a C program. The C program "simulates" your design when it executes on a host machine.

-Rohit</description>
		<content:encoded><![CDATA[<p>Most FV tools dont simulate the design. </p>
<p>There are tools that support both  Simulation Static-Equivalency-checks. Magellan from synopsys comes to mind.</p>
<p>FV tools essentially compare logic cones between &#8220;cut points&#8221;. Cut points are sequentials and primary outputs. A &#8220;logic cone&#8221; is represented as a BDD (or its present day variant - ROBDD).</p>
<p>Simulation tools are completely different. They compile your design into a C program. The C program &#8220;simulates&#8221; your design when it executes on a host machine.</p>
<p>-Rohit</p>
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