Interfaces in SystemVerilog - 2
SystemVerilog allows tasks and functions to be declared within interface definitions known as interface methods. The task or function has the same syntax as when declared in a module. Using these interface methods, the communication protocol details can be embedded within the interface definition itself.
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interface ahb_bus (input logic ahb_hclk, ahb_hresetn); // Interface can have ports.
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wire [31:0] ahb_hdata;
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wire [31:0] ahb_addr;
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logic ahb_hwrite;
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logic [1:0] ahb_htrans;
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logic [2:0] ahb_hsize;
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logic [2:0] ahb_hburst;
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logic ahb_hready;
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logic [1:0] ahb_hresp;
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// Task defined internal to interface
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task slave_read ( input logic [31:0] raddr);
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// ...
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endtask
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endinterface
Interface methods can also be imported if they are not defined within the interface definition itself. If an interface is connected using modport construct, then the import keyword is used to specify the method. Alternative way is to add the task keyword next to the import and also include function arguments - this is required if the task is exported from an external module.
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interface ahb_bus (input logic ahb_hclk, ahb_hresetn); // Interface can have ports.
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wire [31:0] ahb_hdata;
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wire [31:0] ahb_addr;
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logic ahb_hwrite;
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logic [1:0] ahb_htrans;
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logic [2:0] ahb_hsize;
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logic [2:0] ahb_hburst;
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logic ahb_hready;
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logic [1:0] ahb_hresp;
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modport slave ( import slave_read, // simplest way of importing tasks
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inout ahb_hdata,
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input ahb_haddr,
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input ahb_hsize,
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output ahb_hready,
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---
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);
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// Alternative explicit way
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modport slave ( import task slave_read (input [31:0] addr), // explicit
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inout ahb_hdata,
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input ahb_haddr,
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input ahb_hsize,
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output ahb_hready,
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---
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);
Importing a task or a function through a modport gives the module access to that task by prepending the interface port name to the task name as with other variables. The imported function/task must be declared as automatic in order to be synthesizable.
SV also includes a way to export a task defined in one module to be available to other modules through an interface. For example, if a function is defined in module A and is exported in the modport construct within interface definition using the
It is also possible to define a task or function using extern keyword without associating it with the modport construct.
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interface shb_bus (....)
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---
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extern check_parity (input logic [31:0] data); // Not associated with modport
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modport ahb_slave (...);
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endinterface
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module A (...);
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task check_parity (input logic [31:0] data);
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// --
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endtask
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endmodule
Interfaces can also contain procedural blocks like always, always_ff, parameters and generate statements similar to modules.
Sphere: Related ContentInterfaces in SystemVerilog
Connectivity across different design modules in Verilog
To resolve this issue, SystemVerilog adds a powerful interface construct to encapsulate the communication between blocks i.e. multiple signals are grouped together to form a single port. The signals declared in the interface definition is in a single location so that any changes in the interface can be captured accurately modifying only once instead of multiple modules as in Verilog. All the modules using this interface need only declare a single interface type port rather than multiple signals. An example of SV interface is below
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// AHB Interface Definition
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interface ahb_bus (input logic ahb_hclk, ahb_hresetn); // Interface can have ports.
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// These external signals (hclk, hresetn can be implicitly connected between modules
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wire [31:0] ahb_hdata;
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wire [31:0] ahb_addr;
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logic ahb_hwrite;
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logic [1:0] ahb_htrans;
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logic [2:0] ahb_hsize;
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logic [2:0] ahb_hburst;
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logic ahb_hready;
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logic [1:0] ahb_hresp;
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endinterface
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// Top level Module
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module ahb_top (input logic ahb_hclk, ahb_hresetn);
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ahb_bus bus (
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.ahb_hclk(ahb_hclk),
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.ahb_hresetn(ahb_hresetn) ); // instance of interface
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arm_core arm_inst (
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// ahb_bus ports
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.bus (bus),
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// other ports
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.port1 (port1) // not part of the interface
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... );
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ahb_slave ahb_slave0 (
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.bus (bus) );
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dma_master dma_master_inst (
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.bus (bus),
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// Other ports
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---
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);
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on_chip_mem on_chip_mem_inst (
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.bus (bus),
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// Other ports
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--
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);
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endmodule
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// Module Definitions
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module arm_core (
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ahb_bus bus, // interface port
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// other ports
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input logic port1
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);
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// functionality
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endmodule
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module ahb_slave (
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ahb_slave bus
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);
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logic [1:0] ahb_hsel;
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logic [31:0] slave_address;
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// functionality
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// Referring signals inside interface requires using interface port name
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assign bus.ahb_addr = (ahb_hsel == 2'b0) ? slave_address; 'z;
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endmodule
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module dma_master (
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ahb_bus bus;
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// Other ports
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---
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);
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// functionality
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endmodule
An interface can also have tasks, functions, parameters, procedural blocks and type declarations to aid in defining the communication protocol. SV interface cannot have a design hierarchy i.e. no modules can be instantiated in the interface. A modport constructs is provided to define the direction for interface port for different modules. Selecting the appropriate modport for each module can be accomplished during either module definition or during module instance as shown in example below.
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interface ahb_bus (input logic ahb_hclk, ahb_hresetn); // Interface can have ports.
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wire [31:0] ahb_hdata;
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wire [31:0] ahb_addr;
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logic ahb_hwrite;
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logic [1:0] ahb_htrans;
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logic [2:0] ahb_hsize;
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logic [2:0] ahb_hburst;
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logic ahb_hready;
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logic [1:0] ahb_hresp;
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modport master ( inout ahb_hdata,
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output ahb_haddr,
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output ahb_hsize,
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input ahb_hready,
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---
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);
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modport slave ( inout ahb_hdata,
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input ahb_haddr,
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input ahb_hsize,
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output ahb_hready,
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---
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);
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endinterface
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module ahb_top (.. );
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ahb_bus bus (...);
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dma_master dma_master_inst (bus.master); // Use the master modport view
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ahb_slave ahb_slave0 (bus.slave); // Use the slave modport view
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endmodule
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// Alternatively, modport construct can be used in module definition
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module ahb_slave (ahb_bus.master bus);
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endmodule
If no modport is associated with a module, by default all net types are inout and all variable types are ref.
A generic interface port defines the port type using the keyword interface instead of using a name of a specific interface type - the advantage is being able to connect the module to different interfaces. Unlike Verilog, no interface port can be left unconnected and SV .name and .* connection rules can be also be used for interface instances.
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module ahb_slave (interface bus); // generic interface port
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ahb_slave ahb_slave0 (bus.slave);
Procedural Statements and Operators in SystemVerilog
Verilog
Enhanced if-else
SV adds unique and priority keywords which can be used before an if clause. A priority if indicates that the logic will be intrepreted in the order listed - i.e. like priority encoder. A unique if indicates that all the expressions in the if-else are mutually exclusive i.e. only one of the expressions is true at any given time. These keywords make the design intent more intuitive and aid synthesis tools infer priority encoder logic only when required. If no condition matches with either of these keywords without an explicit else, it results in a runtime error.
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logic [3:0] mode_sel;
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always_comb begin
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unique if (mode_sel == 4'b0001) out = in1; // unique - mutually exclusive conditions, can be executed in parallel
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else if (mode_sel == 4'b0010) out = in2;
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else if (mode_sel == 4'b0100) out = in3;
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else if (mode_sel == 4'b1000) out = in4;
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end
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always_comb begin
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priority if (mode_sel == 4'b0001) out = in1; // priority - sequential order, first true expression takes precedence
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else if (mode_sel == 4'b0010) out = in2;
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else if (mode_sel == 4'b0100) out = in3;
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else if (mode_sel == 4'b1000) out = in4;
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end
Enhanced case statements
Similar to if-else statements, SV supports priority and unique keywords for case, casex and casez statements also. For synthesis, the unique case is similar to enabling the full_case and parallel_case pragmas and priority case is similar to enabling the full_case. However, by including these keywords in the SV language rather than use synthesis pragmas, any simulation/synthesis mismatches in how tools intrepret the logic can be avoided.
Enhanced for loops
In Verilog, the variable used in a for loop expression should be declared prior to the loop. Also, if multiple for loops are running concurrently, separate variables need to be used. SV simplifies the for loops by allowing to declare the variable in for loop expression itself.
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always_ff @(posedge clk) begin : label_count // SV allows named begin-end blocks
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for (int i = 0; i <16; i++) // automatic variable int, i visible only within for loop
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count = count + incr[i]
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end : label_count
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//foreach loop construct
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logic [15:0] parity;
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logic [15:0] [7:0] data;
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foreach (parity[i]) parity[i] = ^data[i]; // generates parity for each data byte
SV adds a foreach loop construct which can be used to iterate over elements of single and multidimensional arrays without specifying the array dimension. SV also adds continue, break and return statements like C. SV also supports labels before any procedural statement.
SV supports a final block that is executed at the end of simulation time (unlike initial time) and is used to display statistical information about the simulation using $display.
Operators
SV includes increment (++) and decrement (--) operators similar to C - they can be used to post-increment or pre-increment a variable. The increment and decrement operators behave as blocking assignments and should be used only for combinatorial blocks to avoid race conditions i.e. the ++ or -- operators should not be used in always_ff blocks.
SV supports C like assignment operators like +=, ^=, !=, *=, <<= etc. These assigment operators behave like blocking assignments like the above. SV adds two new comparison operators ==? and !=? in addition to == and === operators.
The ==? referred to as wildcard equality operator makes a bit wise comparison of two operands but any logic X or Z in the right operand is treated as a wildcard and matches any value in the LHS operand's corresponding bit position.
In addition, SV supports inside keyword to test if a variable matches anywhere within a set of values.
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logic [2:0] count;
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if (count inside (3'b001, 3'b010, 3'b100)) // similar to if ((count==3'b001) || (count==3'b010)..)
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int count [0:31];
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if (100 inside (count)); // can also be an array