THE VLSI HOMEPAGE

Need for Logic Built-in Self Test (BIST)

Traditional scan requires large number of vectors to sensitize the design, runs at a maximum frequency of 50 MHz and is limited by number of channels supported by the tester. All these add to tester time that varies from 25 to 50 cents per second. Many designs integrate Logic BIST to overcome these limitations and reduce cost of testing.

Logic BIST, in brief words, involves driving control signals from an in-built controller, generating pseudo-random patterns on the chip, compact the responses from these patterns on the chip - All these occurs at-speed reducing the interface to the tester, the tester memory and also tester time.

Logic BIST Architecture

Logic BIST Architecture

The figure above shows the architecture of Logic BIST that is based on the traditional scan based architecture (known as STUMPS model). The primary instances in this model are:

• Pseudo-random Pattern Generator (PRPG) - this is implemented using linear feedback shift registers (LFSR) to generate pseudo-random patterns to stimulate the design. The LFSR is “maximal length” by nature which means that it visits each and every state before repeating the sequence.

• The Phase shifter block ensures that a large number of scan chains in the design are driven using a short LFSR by using phase-shifting techniques. This phase shifting also removes any inter-channel dependence between input channels. There are muxes at the input of the scan chains to select either traditional scan inputs (muxed-scan) or from PRPG to achieve more fault coverage.

• Space Compactor compresses the output of these scan chains using XOR logic before feeding the compressed outputs to Multiple Input Signature Register (MISR). The MISR outputs are then compared internally with an on-chip reference signature or are scanned out of primary pins.

• A BIST controller that controls the generation of clock control and scan enable signals apart from counters to track the shift cycles. A TAP interface is also integrated in the controller to initiate logic BIST through JTAG.

The shift pattern is determined by the longest scan chain path and also the number of capture clocks (usually one) in the design. Patterns from PRPG are shifted into the scan chains while simultaneously being compressed at the other end into MISR for better utilization.

The design requirements are stringent - no unknown “X” sources (like memories, non-scannable flip-flops), design should be pseudo random pattern testable with minimal area overhead. Any “X” sources can cause corruption of MISR outputs and hence control and test points need to be added in the design. The advantages far outweigh the disadvantages for complex multi-million gate designs - LogicVision’s LogicBIST and Mentor’s TestKompress are two well-known DFT tools for logic BIST.

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