http://vlsihomepage.com/2007/09/22/dft-traditional-scan/ A Practical guide to VLSI Design and Verification.. Mon, 06 Oct 2008 16:50:37 +0000 http://wordpress.org/?v=2.2.2 http://vlsihomepage.com/2007/09/22/dft-traditional-scan/#comment-8 Logic BIST | THE VLSI HOMEPAGE Tue, 25 Sep 2007 15:22:28 +0000 http://vlsihomepage.com/2007/09/22/dft-traditional-scan/#comment-8 [...] Traditional scan requires large number of vectors to sensitize the design, runs at a maximum frequency of 50 MHz and is limited by number of channels supported by the tester. All these add to tester time that varies from 25 to 50 cents per second. Many designs integrate Logic BIST to overcome these limitations and reduce cost of testing. [...] […] Traditional scan requires large number of vectors to sensitize the design, runs at a maximum frequency of 50 MHz and is limited by number of channels supported by the tester. All these add to tester time that varies from 25 to 50 cents per second. Many designs integrate Logic BIST to overcome these limitations and reduce cost of testing. […]

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