THE VLSI HOMEPAGE

Overview

Design for Testability (DFT) is one of the critical requirements in a design - additional test logic is added to detect any manufacturing defects such as opens/shorts on a silicon die. A chip or a die can be tested at various levels ( at wafer level, package level, board level, system level or in the field). By detecting the manufacturing defects beforehand, the manufacturing costs can be lowered.

Various fault models exist to model the defects such as “stuck-at” faults - where a particular node is either stuck at zero or one and a vector should excite the node to it’s opposite value to detect the fault. Delay fault models help in detecting sequential faults that affect timing but not the functionality.

Controllability and Observability are key concepts to DFT. Controllability is the ability to set or reset each and every internal node in the design while Observability is the ability to observe (either directly or indirectly) any node’s state.

For example, one of the requirements for DFT is that all clocks and resets in the design must be controllable from the pins - this involves adding multiplexers with additional test control logic. This falls under the Ad-hoc testing category.

Designs also integrate testability features like traditional scan, Memory BIST (Built-in Self Test) and Repair, Boundary scan (JTAG), Logic BIST and IDDQ to ease testing at wafer/package level. These features are exercised using test vectors that are generated by ATPG (Automatic Test Pattern Generation) tools. Algorithms such as D-Algorithm, PODEM, SCOAP aid the ATPG tool in reducing the number of required test vectors and thus the tester time.

Fault coverage is the measure of effectiveness of test vectors exercised on the design. In most designs, a fault coverage of atleast 98% is mandatory before taping out.

We will look at each one of the DFT features in detail in another post.

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