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	<title>Comments on: Setup and Hold times</title>
	<link>http://vlsihomepage.com/2007/09/13/setup-and-hold-times/</link>
	<description>A Practical guide to VLSI Design and Verification..</description>
	<pubDate>Mon, 06 Sep 2010 16:51:42 +0000</pubDate>
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	<item>
		<title>By: Nigam</title>
		<link>http://vlsihomepage.com/2007/09/13/setup-and-hold-times/#comment-5031</link>
		<author>Nigam</author>
		<pubDate>Sun, 05 Jul 2009 03:40:00 +0000</pubDate>
		<guid>http://vlsihomepage.com/2007/09/13/setup-and-hold-times/#comment-5031</guid>
		<description>Thanks guys for spotting the errors.</description>
		<content:encoded><![CDATA[<p>Thanks guys for spotting the errors.</p>
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	<item>
		<title>By: JP</title>
		<link>http://vlsihomepage.com/2007/09/13/setup-and-hold-times/#comment-4432</link>
		<author>JP</author>
		<pubDate>Mon, 15 Jun 2009 01:07:55 +0000</pubDate>
		<guid>http://vlsihomepage.com/2007/09/13/setup-and-hold-times/#comment-4432</guid>
		<description>The setup margin for the 2nd case is 0.950 ns and hold margin is 5.1 - 0.35 = 4.75ns</description>
		<content:encoded><![CDATA[<p>The setup margin for the 2nd case is 0.950 ns and hold margin is 5.1 - 0.35 = 4.75ns</p>
]]></content:encoded>
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	<item>
		<title>By: Andrea</title>
		<link>http://vlsihomepage.com/2007/09/13/setup-and-hold-times/#comment-3785</link>
		<author>Andrea</author>
		<pubDate>Tue, 19 May 2009 14:22:52 +0000</pubDate>
		<guid>http://vlsihomepage.com/2007/09/13/setup-and-hold-times/#comment-3785</guid>
		<description>also hold margin in the first case should be fixed</description>
		<content:encoded><![CDATA[<p>also hold margin in the first case should be fixed</p>
]]></content:encoded>
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	<item>
		<title>By: Andrea</title>
		<link>http://vlsihomepage.com/2007/09/13/setup-and-hold-times/#comment-3784</link>
		<author>Andrea</author>
		<pubDate>Tue, 19 May 2009 14:12:51 +0000</pubDate>
		<guid>http://vlsihomepage.com/2007/09/13/setup-and-hold-times/#comment-3784</guid>
		<description>Nice and clear, setup violation is -0.95 ns, not -1.05 ns</description>
		<content:encoded><![CDATA[<p>Nice and clear, setup violation is -0.95 ns, not -1.05 ns</p>
]]></content:encoded>
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	<item>
		<title>By: Girish Pai</title>
		<link>http://vlsihomepage.com/2007/09/13/setup-and-hold-times/#comment-1260</link>
		<author>Girish Pai</author>
		<pubDate>Sun, 04 Jan 2009 08:26:24 +0000</pubDate>
		<guid>http://vlsihomepage.com/2007/09/13/setup-and-hold-times/#comment-1260</guid>
		<description>Hi Nigam,

Brilliant explaination. But i have one doubt regarding hold time calculation for 2nd case where u have got the final answer as 6.75 ns. 

Shouldnt the data expected time for hold be calculated with respect to negative edge of CKB as reg 2 negative edge triggered. 

In your case, u have calculated the expected time with respect to positive edge of CKB.</description>
		<content:encoded><![CDATA[<p>Hi Nigam,</p>
<p>Brilliant explaination. But i have one doubt regarding hold time calculation for 2nd case where u have got the final answer as 6.75 ns. </p>
<p>Shouldnt the data expected time for hold be calculated with respect to negative edge of CKB as reg 2 negative edge triggered. </p>
<p>In your case, u have calculated the expected time with respect to positive edge of CKB.</p>
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