Comments on: Clock Dividers http://vlsihomepage.com/2007/09/04/clock-dividers/ A Practical guide to VLSI Design and Verification.. Sun, 01 Aug 2010 09:00:38 +0000 http://wordpress.org/?v=2.2.2 By: Bubleek http://vlsihomepage.com/2007/09/04/clock-dividers/#comment-5868 Bubleek Fri, 21 Aug 2009 10:36:52 +0000 http://vlsihomepage.com/2007/09/04/clock-dividers/#comment-5868 The proposed option is certainly not bad, but not always at the exit of the scheme does not always beat 50% duty cycle, but always clearly divided by 3. 50% duty cycle only works if the input frequency will be 50% duty cycle! The proposed option is certainly not bad, but not always at the exit of the scheme does not always beat 50% duty cycle, but always clearly divided by 3. 50% duty cycle only works if the input frequency will be 50% duty cycle!

]]> By: Aditya Bankar http://vlsihomepage.com/2007/09/04/clock-dividers/#comment-1591 Aditya Bankar Tue, 10 Feb 2009 13:17:57 +0000 http://vlsihomepage.com/2007/09/04/clock-dividers/#comment-1591 Hi, In the div-3 circuit (50% duty cycle) you can avoid the combinational feedback shown in figure. In your 33/66 div-3 circuit if you implement this: Q1 OR (CLK AND Q2) then you get a 50% duty cycle div-3 clock at the output. You don't need a circuit which is that complicated. Thanks, Aditya Hi,

In the div-3 circuit (50% duty cycle) you can avoid the combinational feedback shown in figure. In your 33/66 div-3 circuit if you implement this: Q1 OR (CLK AND Q2) then you get a 50% duty cycle div-3 clock at the output. You don’t need a circuit which is that complicated.

Thanks,
Aditya

]]>