THE VLSI HOMEPAGE

Clock dividers are common in ASIC design where an internal clock needs to be generated by using divide-by-n logic on a reference clock source. We will look at divide-by-2 and divide-by-3 circuits with and without 50% duty cycle in this post.

Divide-by-two clock

A divide-by-two clock that is synchronous to the clock source is used very widely. The figure below shows a simple divide-by-2 circuit and the corresponding waves.

Divide-by-2 Circuit with 50% duty cycle

Divide-by-3 clock with 33/66 duty cycle

A divide-by-3 clock can be generated from a clock source as shown in the figure below. Note that the source clock has a 50% duty cycle while the divide-by-three output does not.

Divide-by-3 clock with 33/66 duty cycle

Divide-by-3 clock with 50% duty cycle

The above circuit can be modified to generate a divide-by-3 clock with 50% duty cycle. This requires clock gating and should be avoided as it can generate glitches in the design. The first flipflop in the circuit generates the high transition while the second flipflop generates the low transition when the clock goes low to give a 50% duty cycle.

Divide by 3 clock with 50% duty cycle

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