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Clock Dividers

Posted in Digital Design by Nigam on the September 4th, 2007

Clock dividers are common in ASIC design where an internal clock needs to be generated by using divide-by-n logic on a reference clock source. We will look at divide-by-2 and divide-by-3 circuits with and without 50% duty cycle in this post.

Divide-by-two clock

A divide-by-two clock that is synchronous to the clock source is used very widely. The figure below shows a simple divide-by-2 circuit and the corresponding waves.

Divide-by-two circuit

 

Divide-by-2 Circuit with 50% duty cycle

Divide-by-3 clock with 33/66 duty cycle

A divide-by-3 clock can be generated from a clock source as shown in the figure below. Note that the source clock has a 50% duty cycle while the divide-by-three output does not.

Divide by 3 clock

Divide-by-3 clock with 33/66 duty cycle

Divide-by-3 clock with 50% duty cycle

The above circuit can be modified to generate a divide-by-3 clock with 50% duty cycle. This requires clock gating and should be avoided as it can generate glitches in the design. The first flipflop in the circuit generates the high transition while the second flipflop generates the low transition when the clock goes low to give a 50% duty cycle.

Divide by 3 clock with 50% duty cycle

Divide by 3 clock with 50% duty cycle

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    • 2 Responses to 'Clock Dividers'

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    1. Aditya Bankar said,

      on February 10th, 2009 at 1:17 pm

      Hi,

      In the div-3 circuit (50% duty cycle) you can avoid the combinational feedback shown in figure. In your 33/66 div-3 circuit if you implement this: Q1 OR (CLK AND Q2) then you get a 50% duty cycle div-3 clock at the output. You don’t need a circuit which is that complicated.

      Thanks,
      Aditya

    2. Bubleek said,

      on August 21st, 2009 at 10:36 am

      The proposed option is certainly not bad, but not always at the exit of the scheme does not always beat 50% duty cycle, but always clearly divided by 3. 50% duty cycle only works if the input frequency will be 50% duty cycle!

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