THE VLSI HOMEPAGE

A dual stage synchronizer cell ensures that the signal remains stable in the sampling clock domain but that is not enough. For example, in the case of a fast source clock to slow destination clock transfer, the signal transition may be lost if the source clock does not hold the signal long enough for the destination clock to sample. On the other hand, if the destination clock is slow, it can sample the signal more than once. Another pitfall is to synchronize both data and strobe (data_valid) signals causing a race condition as the data/strobe signal can change at different times based on PVT. Thus, synchronizers should not be used on individual bits but only on the control (valid or enable) signal.
A more robust and simple synchronization technique to solve these issues is known as toggle synchronizer or a pulse synchronizer. The toggle synchronizer has a signal synchronization stage and a req-ack protocol - i.e. the destination clock domain acks the source clock domain on reception of the signal transition change. The source clock domain signals another change in the strobe (valid) signal only on receiving this ACK. By using the change in signal’s level (transition) rather than level itself to communicate through the synchronizer makes this design robust.

A REQ path logic for the toggle synchronizer is depicted in the figure below - a signal transition in the source clock domain is translated to a signal pulse one cycle wide in the destination clock domain. By mirroring this REQ logic for a transfer from destination clock domain to source clock domain completes the handshaking scheme - a REQ-ACK protocol.

This scheme is elegant because there is no dependency on clock frequency relationships in source/destination domains. One caveat is that the input pulses must have a minimum spacing of atleast two destination synchronizer clock cycles for proper operation. If the input pulses are very close, there is a risk of the output pulse being longer than one clock cycle or not detecting the second transition at all.

This scheme can also be used to self clear interrupts where the CPU’s interrupt service routine writes to a interrupt clear register in the destination clock domain. In such a scenario, only the REQ path logic is necessary.

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