Comments on: ASIC Design Flow - II http://vlsihomepage.com/2007/08/28/asic-design-flow-ii/ A Practical guide to VLSI Design and Verification.. Mon, 06 Oct 2008 16:48:21 +0000 http://wordpress.org/?v=2.2.2 By: Nigam http://vlsihomepage.com/2007/08/28/asic-design-flow-ii/#comment-224 Nigam Sat, 22 Mar 2008 06:41:09 +0000 http://vlsihomepage.com/2007/08/28/asic-design-flow-ii/#comment-224 thanks Shwetha ! The post above is based on my industry exposure in part and partly books/papers I have referred to in the past. I wish I could point to any one book that covers ASIC flow in detail. Bening & Foster's "principles of verifiable rtl design" is one good book I would recommend. thanks Shwetha !

The post above is based on my industry exposure in part and partly books/papers I have referred to in the past. I wish I could point to any one book that covers ASIC flow in detail.

Bening & Foster’s “principles of verifiable rtl design” is one good book I would recommend.

]]> By: Shwetha http://vlsihomepage.com/2007/08/28/asic-design-flow-ii/#comment-214 Shwetha Thu, 20 Mar 2008 13:02:34 +0000 http://vlsihomepage.com/2007/08/28/asic-design-flow-ii/#comment-214 Nigam, This is the article that a beginner would like to appreciate. May I ask for the links/books that you have referred to that has given an outcome as good as the above? Thanks Shwetha Nigam,
This is the article that a beginner would like to appreciate.
May I ask for the links/books that you have referred to that has given an outcome as good as the above?

Thanks
Shwetha

]]> By: chipdesignart http://vlsihomepage.com/2007/08/28/asic-design-flow-ii/#comment-18 chipdesignart Wed, 17 Oct 2007 11:24:53 +0000 http://vlsihomepage.com/2007/08/28/asic-design-flow-ii/#comment-18 Hi Nigam, Good article , really appreciate your efforts. Regarding ASIC design flow is explained in detailed with the tools used and their roles at each stage is explained. Request you to check this . http://www.vlsichipdesign.com/vlsidesignflow.html Hi Nigam,

Good article , really appreciate your efforts.
Regarding ASIC design flow is explained in detailed with the tools used and their roles at each stage is explained. Request you to check this .
http://www.vlsichipdesign.com/vlsidesignflow.html

]]> By: Nigam http://vlsihomepage.com/2007/08/28/asic-design-flow-ii/#comment-13 Nigam Fri, 12 Oct 2007 09:48:35 +0000 http://vlsihomepage.com/2007/08/28/asic-design-flow-ii/#comment-13 hi Rohit, I agree - the design flow is customized as per the chip requirements, IP integration, the market it is catering to etc. There is no one flow that fits all. As for "real" chips - yes, based on my exposure, I have seen chips conforming to this flow - standard products catering to consumers for example. The points you make are all valid for high-speed designs (network processors for example), experience in which I lack :) regards, Nigam hi Rohit,

I agree - the design flow is customized as per the chip requirements, IP integration, the market it is catering to etc. There is no one flow that fits all.

As for “real” chips - yes, based on my exposure, I have seen chips conforming to this flow - standard products catering to consumers for example.

The points you make are all valid for high-speed designs (network processors for example), experience in which I lack :)

regards,
Nigam

]]> By: RN http://vlsihomepage.com/2007/08/28/asic-design-flow-ii/#comment-10 RN Thu, 11 Oct 2007 06:43:37 +0000 http://vlsihomepage.com/2007/08/28/asic-design-flow-ii/#comment-10 This is "one" design flow. If you want to design any kind of a "real" chip, you are going to have register files and caches. You will need a design flow for the small signal arrays and RFs. And if you really want performance, your datapath should be hand designed. Have you ever tried to route a datapath block lately? I havent, and when I evaluated tools a while ago, I was less than impressed with the datapath design features of Synthesis/APR tools. -RN This is “one” design flow.

If you want to design any kind of a “real” chip, you are going to have register files and caches. You will need a design flow for the small signal arrays and RFs.

And if you really want performance, your datapath should be hand designed. Have you ever tried to route a datapath block lately? I havent, and when I evaluated tools a while ago, I was less than impressed with the datapath design features of Synthesis/APR tools.

-RN

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